This application claims a foreign priority from German patent application no. 101 06 403.9, filed Feb. 12, 2001, and the contents of that application are incorporated by reference herein.
The invention concerns a device for converting a digital input signal string having an input-sampling rate into a digital output signal string having an output-sampling rate that is higher than the input-sampling rate. Such a device is generally called a resampler. The increase in the sampling rate is called up-sampling. The invention also relates to a corresponding method.
A resampler for down-sampling is known from European patent document EP 0 665 546 A2, for example. In a resampler, a relationship between the input-sampling rate and the output-sampling rate must first be determined. In the aforementioned document, this is accomplished through a gate time measurement. The sampled values for the output sample times specified by the output-sampling rate are interpolated in an interpolator from the input signal string. In this regard, the interpolator is controlled by a detected sampling rate ratio. Since determination of the sampling rate ratio is subject to measuring inaccuracy, buffering takes place in a buffer store, for example a FIFO, at the output of the interpolator in the case of down-sampling and at the input of the interpolator in the case of up-sampling. In this context, the integral behavior of the FIFO memory is exploited. EP 0 665 546 A1 proposes regulating the sampling rate ratio that controls the interpolator as a function of the fill level, or condition, of the buffer store.
The regulation of the sampling rate ratio (relationship) as a function of the fill level of the buffer store proposed in EP 0 665 546 A2 has the disadvantage that when the fill level of the buffer store changes, a group propagation delay of the digital signal through the resampler changes. In an application, such as in mobile radio telephony, larger changes in buffer store fill level (e.g. +/xe2x88x921), that is a change by one storage unit, are not tolerable since they lead to variations in propagation delay of the signal through the resampler. With the buffer store fill level controller proposed in EP 0 665 546 A1, deviations in a clock rate ratio are detected relatively late, after a relatively large detuning of the ratio has already taken place. This leads to relative large interpolation errors due to incorrect sampling times. Up-sampling is not possible with this resampler without further measures.
A resampler for down-sampling is described in the not-published German patent document DE 101 02 166 A1 by the same inventor and the same assignee. Conversion from the down-sampling described in this document to up-sampling is not possible without the knowledge contained in the present invention.
It is an object of this invention is to provide a device (resampler) and a method (resampling method) for the conversion of a digital input signal string with an input-sampling rate into a digital output signal string with a higher output-sampling rate, which device and/or method functions with high precision and can be implemented with limited expense.
The object is attained with regard to the device through the features of claim 1, and with regard to the method through the features of claim 9. The dependent claims contain advantageous refinements of the device and/or the method.